>
  VLSI TRAINER KIT
INTRODUCTION
The FPGA trainer is a versatile tool for experimenting with standard FPGAs / CPLDs with provision to mount a daughter board on the base board.

The daughter board comes with various FPGA and CPLD options from XILINX and ALTERA. It also provides test pins to connect Pattern generator and Logic analyzer to connect various Inputs and Outputs of the FPGA. Apart from this the base board contains various interface options to readily connect switches and displays etc. A number of tutorial exercises have been worked out. An exhaustive easy to follow documentation has been provided for quick learning of various environments, schematic and VHDL programming.

 BASE BOARD

 

32 Toggle switches for I/P selection with 32 LEDs to indicate switch status

32 LEDs connected to output ports of the FPGA

Two line X 16 Alpha-Numeric LCD display with back-light

Four digit 7-segment display

4 X 4 key matrix

2 nos. of Push button switches

 

On board 10 MHz oscillator

10 MHz clock and one of four different frequency clocks (5Mhz, 1Mhz, 500Khz and 100Khz)

User I/Os available for Pattern generator and Logic Analyzer connection

Standard VGA, PS-2 and RS-232 serial interface connectors are provided

On-board different supply voltage generator to match the multi-volt with LED indication

FPGA/CPLD of different makes (1.8V, 2.5V, 3.3V, 5V) with LEDs to identify the card type

26-pin FRC connector for connecting to ALS standard interface boards like Stepper motor, ADC, DAC, Traffic light controller, Elevator, Printer interface etc

Four sets of 20 X 2 female berg connectors to plug the child card

 DAUGHTER BOARD - 1

 

XILINX XC3S50 - FPGA IC with 1 MB ROM for stand alone programming

Push-button switch to re-initialise the FPGA

Four sets of 20 X 2 berg connectors for plugging on to the main board

JTAG connector for boundary scan programming

Mode selection jumpers

 DAUGHTER BOARD - 2

 

XILINX XC9572PC84 - CPLD IC

Four sets of 20 X 2 berg connectors for plugging on to the main board

JTAG connector for boundary scan programming

 DAUGHTER BOARD - 3

 

ALTERA EP1C6PQ240C8 - FPGA IC. With 1 MB ROM for stand alone programming

Push-button switch to re-initialise the FPGA

Four sets of 20 X 2 berg connectors for plugging on to the main board

JTAG connector for boundary scan programming

Mode selection jumpers

 DAUGHTER BOARD - 4

 

XILIN X FPGA X C3S400 with N V ROM

 

ALS-SDA-FPGA/CPLD – 02 TRAINER

   

Four digit 7 segment displays connected through 10 Pin FRC connectors to FPGA/CPLD port pins.

4 X 4 key matrix connected through 10 Pin FRC connectors to FPGA/CPLD port pins.

10 Mhz, 5 Mhz, 1Mhz,500Khz, 100Khz-five different clock frequencies.

Onboard multiple Dc supply voltage generator with LED indication.

Four sets of 30X2 Male Berg connectors to plug the daughter board.

A number of sample program for experiments and to demonstrate the interfacing capalbilites.

26 pin FRC cable for connecting to ALS standard interface like ADC, DAC, DC motors etc.

Number of flying leads are provided for external connectors.

Four numbers of 10 Pin FRC cables.

 

DAUGHTER BOARD -1 XC3S50 BOARD

NVROM for stand alone programming

Ten 10 Pin FRC connectors around the daughter board for connection to the on board interfaces like 7 segment LCD etc.

JTAG connector (10 pin FRC connector/6 Pin reliamate)for boundary scan programming

Mode selection jumpers

Four sets of 30X 2 female berg connector for plugging

On the main road

 DAUGHTER BOARD-2 XC9572 BOARD

Xilinix SC9572PC84 CPLD

Seven 10 Pin FRC connectors around the daughter

Board for connection to the on board interfaces like

Key matrix, LCD etc.,

JTAG connector (10 PIN FRC connector/6 PIN reliamate) for boundary scan programming

Four sets of 30 X 2 female Berg connector for

Plugging on to the main board

 DAUGHTER BOARD 3 XC3S400 BOARD

Xilinx SC3S400 FPGA

NVROM for stand alone programming

Ten 10 PIN FRC connectors around the daughter board for connection to the on board interfaces

Like 7 segment, LCD etc.,

JTAG connector (10 PIN FRC connector/6 PIN reliamate)for boundary scan programming

Mode selection jumpers

Four sets of 30 X 2 female berg connector for plugging on to the main board

ALS-SDA-FPGA/CPLD – 03 TRAINER

ALS-SDA-FPGA-03 TRAINER is a toll for understanding the capabilities of an industry standard FPGA. The board contains various interface options including Switches LEDs, LCD, seven segment display, key matrix, relay, buzzer, Traffic light simulator, Dc motor interface.

16 inputs using DIP switches.

16 outputs through output sports of FPGA connected to LEDs

16x2 Alpha-Numeric LCD display with back-light.

Four – digit 7 segment displays.

4x4 key matrix

10Mhz clock and one of four different clocks (5Mhz, 1Mhz,500KHz,100KHz) on-board Buzzer.

On- board DPDT relays.

On-board Traffic light Simulator

On-board Dc motor interface with 2 pin connection to external DC motor.

On-board multiple Dc supply voltage generator

26 pin FRC cable for connecting to ALS standard interfaces like ADC, DAC Elevator etc.

A number of sample programs to demonstrated the interfacing capabilities.

 
Versatile Hardware Design Lab
Tk Base

TKBase is an Universal training tool aimed at enabling mainstream engineers to learn complete Digital/μC based technology from 89C51 to FPGA/CPLD/PSoC/ARM7 platform.

TKBase can integrate all necessary hardware test tools like Logic Analyzer, Pattern Generator, configured μC Disassembler, Compilers/Assemblers/Debuggers, μC/ FPGA/ CPLD/SoC Daughter Boards, all under an single unified environment.

Compilers, Converters, Debuggers & Lab Experiments are all available for Embedded ’C/C++/VHDL’ codes to allow engineers to interactively learn, design, burn, test and interface any popular embedded system easily.

• Universal VLSI /μC Trainer
• Multi-Vendor FPGA/CPLD/μC
• PLCC, PQFP,TQFP devices
• Upto 240 pin devices
• All I/O with VCC/GND links.
• Support’s 1.8V to 5V devices
• Vendor Specific Gate density
• JTAG Programming cable
• Parallel/Serial/USB/SPI/CAN
• PS2 Mouse & Keyboard I/F
• Traffic Light/Stepper interface
• On board Clock 100K-10Mhz
• 16x2 LCD Display
• 4 Digit 7-SEG Display
• 4x4 Matrix KeyPad
• I2C EEProm & RTC
• Serial ADC / DAC with Pot.

Pattern Generator (Optional)

  • 32 Channels
  • Expandable to 48 Channel
  • 128K bit Patterns
  • Single strp mode
  • Loop mode

Logic Analyzer (Optional)

  • 100Mhz Speed
  • 32 Channels
  • 128K Memory/Channel
  • Mixed Mode Analysis
  • 65535 Event Counter
  • 65535 Count Delay
  • 16 Trigger Words
  • 4 Level Triggering with Delay
  • 3 External Clock's

Daughter Boards (Optional)

  • 89C51 Daughter Board
  • ARM7 Daughter Board
  • CoreMP7 Daughter Board
  • PIC16F877 Daughter Board
  • CPLD Daughter Board
  • FPGA Daughter Board
  • PicoBlaze SoftCore Board
  • PIC SoftCore Board
  • C Compiler / Debugger
  • Real Time Disassembly Support

Complete Courseware

 
   
TK Base—Universal μC / FPGA / CPLD / ARM7 Evaluation board

An integral part of Laboratory training is TKBase - an Universal FPGA/CPLD/μC/ARM7/PSoC -based hardware evaluation kit. TKBase acts as areconfigurable implementation platform to allow rapid interchangeable andinteractive prototype development.
Features:

The TKbase houses a plug-in daughter board containing a target FPGA/CPLD/ μC device. Daughter boards can be easily swapped to supporttraining for variety of devices. The universal concept provides support for multi-vendor devices available in PLCC,TQFP,PQFP packages up to 240 pins. Compilers/Debuggers/Placement and programming tools for the target device is handled by vendor specific device tools. These tools are sourced and installed separately.

TKBase also contains a range of off-chip peripherals such as a 4x4 array Keys, LCD display, LED arrays, DIP switches, serial/parallel/VGA/USB ports, ADC/DAC, RTC & general IO connectors etc. TKBase connects to the user’s PC and follows JTAG standard to download/debug designs on the target device allowing easy access to various onboard peripherals without the need to build a conventional prototype board.

All I/O lines are taken out through berg header’s with jumpered VCC and Ground pins for fast static test. An engineer can now ‘burn & learn’ any port-connected I/O signal lines and buses in real time using our integrated Pattern Generator & Logic Analyzer.

 


Real Time Stimulation— Hardware Test Bench

Our pioneering new design technology now brings together the world of Logic Analysis and Pattern Generation in a single, integrated design environment. This new technology enables engineers to have more options than ever before for real-time testing of FPGA/CPLD/μC/ARM7/PSoC systems.

Most popular processor cores and its associated compilers, assemblers, linkers and debuggers are fully supported. Processor specific Disassembly adapters provide highly optimized ‘C’ or Assembly source file trace.

TKBase used in conjunction with LG320’s Integrated Pattern Generator's allows us to deliver a system that enables rapid implementation, stimulation and testing of complete digital systems without the need for extensive software synthesis and verification. The verification is of an order of magnitude much faster than just software simulation - based approaches.

The LG320 Logic Analyzer captures live stimulus response, and utilizes the live data to automatically create a test bench. This allows the FPGA/CPLD/ μC/ARM7/PSoC device cores to be exercised at ‘actual hardware speeds’.

LG320’s integrated stimulation takes advantage of the reconfigurable nature of TKBase multi device platform, allowing engineers to try multiple design iteration and minimizing the reliance on time-consuming software only simulation.